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Low Cost ␮P
Supervisory Circuits
ADM705–ADM708
FEATURES
FUNCTIONAL BLOCK DIAGRAMS
Guaranteed RESET Valid with VCC = 1 V
190 ␮A Quiescent Current
Precision Supply-Voltage Monitor
WATCHDOG
WATCHDOG
WATCHDOG
4.65 V (ADM705/ADM707)
TRANSITION
INPUT (WDI)
WATCHDOG
DETECTOR
OUTPUT (WDO)
4.40 V (ADM706/ADM708)
200 ms Reset Pulsewidth
RESET &
Debounced TTL/CMOS Manual Reset Input (MR)
WATCHDOG
TIMEBASE
Independent Watchdog Timer—1.6 sec Timeout
(ADM705/ADM706)
Active High Reset Output (ADM707/ADM708)
GENERATOR
Voltage Monitor for Power-Fail or Low Battery
Superior Upgrade for MAX705–MAX708
POWER-FAIL
Also Available in MicroSOIC Packages
INPUT (PFI)
POWER-FAIL
OUTPUT (PFO)
APPLICATIONS
*VOLTAGE REFERENCE = 4.65V (ADM705), 4.40V (ADM706)
Microprocessor Systems
Computers
Controllers
Intelligent Instruments
Critical ␮P Monitoring
Automotive Systems
Critical ␮P Power Monitoring
GENERATOR
GENERAL DESCRIPTION
The ADM705–ADM708 are low cost µP supervisory circuits.
POWER-FAIL
They are suitable for monitoring the 5 V power supply/battery INPUT (PFI)
POWER-FAIL
OUTPUT (PFO)
and can also monitor microprocessor activity.
The ADM705/ADM706 provide the following functions: *VOLTAGE REFERENCE = 4.65V (ADM707), 4.40V (ADM708)
1. Power-On Reset output during power-up, power-down and brownout conditions. The RESET output remains opera-tional with VCC as low as 1 V.
Two supply-voltage monitor levels are available. The ADM705/ 2. Independent watchdog timeout, WDO, that goes low if the ADM707 generate a reset when the supply voltage falls below watchdog input has not been toggled within 1.6 seconds.
4.65 V, while the ADM706/ADM708 require that the supply 3. A 1.25 V threshold detector for power-fail warning, low fall below 4.40 V before a reset is issued.
battery detection or to monitor a power supply other than All parts are available in 8-lead DIP and SOIC packages. The ADM707 and ADM708 are also available in space-saving 4. An active low debounced manual reset input (MR).
The ADM707/ADM708 differ in that:1. A watchdog timer function is not available.
2. An active high reset output in addition to the active low Information furnished by Analog Devices is believed to be accurate andreliable. However, no responsibility is assumed by Analog Devices for itsuse, nor for any infringements of patents or other rights of third parties One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
which may result from its use. No license is granted by implication or Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
otherwise under any patent or patent rights of Analog Devices.
Fax: 781/326-8703
Analog Devices, Inc., 2000
ADM705–ADM708–SPECIFICATIONS (VCC = 4.75 V to 5.5 V, TA = TMIN to TMAX unless otherwise noted.)
Parameter
Test Conditions/Comments
Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS*
ORDERING GUIDE
Temperature Range
Package Option
VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 VAll Other Inputs . . . . . . . . . . . . . . . . . . –0.3 V to VCC + 0.3 V VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Power Dissipation, N-8 DIP . . . . . . . . . . . . . . . . . . . . 727 mW θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 135°C/W Power Dissipation, SO-8 SOIC . . . . . . . . . . . . . . . . . . 470 mW JA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 110°C/W Industrial (A Version) . . . . . . . . . . . . . . . . . –40°C to +85°C Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . 300°C Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . . 215°CInfrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°CESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >5 kV *Stresses above those listed under Absolute Maximum Ratings may cause perma- nent damage to the device. This is a stress rating only; functional operation of thedevice at these or any other conditions above those listed in the operationalsections of this specification is not implied. Exposure to absolute maximumratings for extended periods of time may affect device reliability ADM705–ADM708
PIN FUNCTION DESCRIPTION
Mnemonic
DIP, SOIC
DIP, SPOC
MicroSOIC
Function
Manual Reset Input. When taken below 0.8 V, a RESET is gener-ated. MR can be driven from TTL, CMOS logic or from a manualreset switch as it is internally debounced. An internal 250 µA pull-upcurrent holds the input high when floating.
0 V. Ground reference for all signals.
Power-Fail Input. PFI is the noninverting input to the Power-FailComparator. When PFI is less than 1.25 V, PFO goes low. If unused,PFI should be connected to GND or VCC.
Power-Fail Output. PFO is the output from the Power-Fail Compara-tor. It goes low when PFI is less than 1.25 V.
Watchdog Input. WDI is a three-level input. If WDI remains eitherhigh or low for longer than the watchdog timeout period, the watch-dog output WDO goes low. The timer resets with each transition atthe WDI input.
Either a high-to-low or a low-to-high transition will clear the counter.
The internal timer is also cleared whenever reset is asserted. Thewatchdog timer is disabled when WDI is left floating or connected toa three-state buffer.
Logic Output. RESET goes low for 200 ms when triggered. It can betriggered either by VCC being below the reset threshold or by a lowsignal on the manual reset (MR) input. RESET will remain lowwhenever VCC is below the reset threshold (4.65 V in ADM705, 4.4 Vin ADM706). It remains low for 200 ms after VCC goes above thereset threshold or MR goes from low to high. A watchdog timeoutwill not trigger RESET unless WDO is connected to MR.
Logic Output. The Watchdog Output, WDO, goes low if the internalwatchdog timer times out as a result of inactivity on the WDI input. Itremains low until the watchdog timer is cleared. WDO also goes lowduring low line conditions. Whenever VCC is below the reset threshold, WDO remains low. As soon as VCC goes above the reset threshold, Logic Output. RESET is an active high output suitable for systemsthat use active high RESET logic. It is the inverse of RESET.
PIN CONFIGURATION
DIP, SOIC DIP, SOIC MicroSOIC
RESET 2 ADM707/ 7 PFO
(Not to Scale)
(Not to Scale)
(Not to Scale)
NC = NO CONNECT
NC = NO CONNECT
ADM705–ADM708
Manual Reset (ADM707/ADM708)
WATCHDOG
WATCHDOG
WATCHDOG
The manual reset input (MR) allows other reset sources, such as TRANSITION
WATCHDOG
INPUT (WDI)
DETECTOR
OUTPUT (WDO)
a manual reset switch, to generate a processor reset. The inputis effectively debounced by the timeout period (200 ms typical).
RESET &
The MR input is TTL/CMOS compatible, so it may also be WATCHDOG
TIMEBASE
GENERATOR
POWER-FAIL
INPUT (PFI)
POWER-FAIL
OUTPUT (PFO)
MR EXTERNALLY
*VOLTAGE REFERENCE = 4.65V (ADM705), 4.40V (ADM706)
DRIVEN LOW
Figure 1. ADM705/ADM706 Functional Block Diagram Figure 3. RESET, MR, and WDO Timing Watchdog Timer (ADM705/ADM706)
The watchdog timer circuit may be used to monitor the activity GENERATOR
of the microprocessor in order to check that it is not stalled in an indefinite loop. An output line on the processor is used to toggle ADM707/
ADM708
the Watchdog Input (WDI) line. If this line is not toggled POWER-FAIL
INPUT (PFI)
POWER-FAIL
within the timeout period (1.6 sec), the watchdog output OUTPUT (PFO)
(WDO) goes low. The WDO output may be connected to anonmaskable interrupt (NMI) on the processor; therefore, if the *VOLTAGE REFERENCE = 4.65V (ADM707), 4.40V (ADM708)
watchdog timer times out, an interrupt is generated. The inter-rupt service routine should then be used to rectify the problem.
Figure 2. ADM707/ADM708 Functional Block Diagram If a RESET signal is required when a timeout occurs, the WDO CIRCUIT INFORMATION
output should be connected to the manual reset input (MR).
Power-Fail RESET Output
The watchdog timer is cleared by either a high-to-low or by a RESET is an active low output that provides a RESET signal to low-to-high transition on WDI. It is also cleared by RESET the Microprocessor whenever the VCC input is below the reset going low; therefore, the watchdog timeout period begins after threshold. An internal timer holds RESET low for 200 ms after the voltage on VCC rises above the threshold. This is intended as a power-on RESET signal for the microprocessor. It allows time CC falls below the reset threshold, WDO is forced low whether or not the watchdog timer has timed out. Normally, for both the power supply and the microprocessor to stabilize this would generate an interrupt, but it is overridden by RESET after power-up. The RESET output is guaranteed to remain valid (low) with VCC as low as 1 V. This ensures that the micro-processor is held in a stable shutdown condition as the power The watchdog monitor can be deactivated by floating the Watchdog Input (WDI). The WDO output can now be used asa low-line output since it will only go low when V In addition to RESET, an active high RESET output is also available on the ADM707/ADM708. This is the complement ofRESET and is useful for processors requiring an active high RESET EXTERNALLY
TRIGGERED BY MR
ADM705–ADM708
Power-Fail Comparator
The power-fail comparator is an independent comparator that
may be used to monitor the input power supply. The comparator’s inverting input is internally connected to a 1.25 V referencevoltage. The noninverting input is available at the PFI input.
This input may be used to monitor the input power supply via a resistive divider network. When the voltage on the PFI input drops below 1.25 V, the comparator output (PFO) goes low, indicating a power failure. For early warning of power failure, the comparator may be used to monitor the preregulator inputsimply by choosing an appropriate resistive divider network.
Valid RESET Below 1 V VCC
The PFO output can be used to interrupt the processor so that The ADM70x family of products is guaranteed to provide a a shutdown procedure is implemented before the power is lost.
valid reset level with VCC as low as 1 V; please refer to the Typi-cal Performance Characteristics. As VCC drops below 1 V, the internal transistor will not have sufficient drive to hold it ON so the voltage on RESET will no longer be held at 0 V. A pull-down POWER-FAIL
resistor as shown in Figure 7 may be connected externally to hold the line low if it is required.
POWER-FAIL PFI
Adding Hysteresis to the Power-Fail Comparator
For increased noise immunity, hysteresis may be added to the power-fail comparator. Since the comparator circuit is non-inverting, hysteresis can be added simply by connecting aresistor between the PFO output and the PFI input as shown in Figure 6. When PFO is low, resistor R3 sinks current from thesumming junction at the PFI pin. When PFO is high, resistorR3 sources current into the PFI summing junction. This resultsin differing trip levels for the comparator. Further noise immu-nity may be achieved by connecting a capacitor between PFIand GND.
INPUT POWER
TO ␮P NMI
Figure 6. Adding Hysteresis to the Power-Fail Comparator ADM705–ADM708–Typical Performance Characteristics
TA = 25؇C
A!
4.50V
1V
1V
500msHo
500ns/DIV
Figure 8. RESET Output Voltage vs. Supply Voltage Figure 11. PFI Comparator Deassertion Response Time TA = 25؇C
A1
4.50V
1V
1V
500msHo
100ns/DIV
Figure 9. ADM707/ADM708 RESET Output Voltage vs.
TA = 25؇C
100ns/DIV
500ns/DIV
Figure 10. PFI Comparator Assertion Response Time Figure 13. RESET, RESET Deassertion ADM705–ADM708
If, in the event of inactivity on the WDI line, a system reset is TA = 25؇C
required, then the WDO output should be connected to the MR Monitoring Additional Supply Levels
2␮s/DIV
It is possible to use the power-fail comparator to monitor asecond supply as shown in Figure 17. The two sensing resistors, Figure 14. ADM705/ADM707 RESET Response Time R1 and R2, are selected so that the voltage on PFI drops below1.25 V at the minimum acceptable input supply. The PFO APPLICATIONS
output may be connected to the MR input so that a RESET is A Typical Operating Circuit is shown in Figure 15. The unregu- generated when the supply drops out of tolerance. In this case, if lated dc input supply is monitored using the PFI input via the either supply drops out of tolerance, a RESET will be generated.
resistive divider network. Resistors R1 and R2 should be selected so that when the supply voltage drops below the desired level(e.g., 8 V), the voltage on PFI drops below the 1.25 V threshold thereby generating an interrupt to the µP. Monitoring the pre- regulator input gives additional time to execute an orderly shutdown procedure before power is lost.
UNREGULATED
Figure 17. Monitoring 5 V and an Additional Supply, VX ␮Ps With Bidirectional RESET
In order to prevent contention for microprocessors with a bidi- rectional reset line, a current limiting resistor should be inserted between the ADM70x RESET output pin and the µP reset pin.
INTERRUPT
This will limit the current to a safe level if there are conflictingoutput reset levels. A suitable resistor value is 4.7 kΩ. If the reset output is required for other uses, it should be buffered as BUFFERED
Microprocessor activity is monitored using the WDI input. This is driven using an output line from the processor. The software routines should toggle this line at least once every 1.6 seconds.
If a problem occurs and this line is not toggled, WDO goes low and a nonmaskable interrupt is generated. This interrupt rou- tine may be used to clear the problem.
Figure 18. Bidirectional I-O RESET ADM705–ADM708
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
8-Lead Plastic DIP
0.39 (9.91)
(6.35) (7.87)
0.30 (7.62)
0.035 ± 0.01
(0.89 ± 0.25)
0.165 ± 0.01
(4.19 ± 0.25)
0.18 ± 0.03
0.125 (3.18)
(4.57 ± 0.76)
0.011 ± 0.003
0.018 ± 0.003
(4.57 ± 0.76)
0° - 15°
(0.46 ± 0.08)
0.10 (2.54)
8-Lead SOIC
0.1968 (5.00)
0.1890 (4.80)
0.1574 (4.00)
0.2440 (6.20)
0.1497 (3.80)
0.2284 (5.80)
0.0688 (1.75)
0.0196 (0.50)x 45°
0.0098 (0.25)
0.0532 (1.35)
0.0099 (0.25)
0.0040 (0.10)
0.0500 0.0192 (0.49)
0.0098 (0.25)
0.0500 (1.27)
0.0138 (0.35)
0.0075 (0.19)
0.0160 (0.41)
8-Lead MicroSOIC
0.122 (3.10)
0.114 (2.90)
0.122 (3.10)
0.199 (5.05)
0.114 (2.90)
0.187 (4.75)
0.0256 (0.65) BSC
0.120 (3.05)
0.120 (3.05)
0.112 (2.84)
0.112 (2.84)
0.043 (1.09)
0.006 (0.15)
0.027 (0.68)
0.002 (0.05)
0.018 (0.46)
0.011 (0.28)
0.027 (0.68)
0.008 (0.20)
0.003 (0.08)
0.015 (0.38)

Source: http://www.ic-cn.com.cn/static/pdf/ADM705AN_AD_148010.pdf